
# This file is used by the simulation model as well as the ispLEVER bitstream
# generation process to automatically initialize the PCSC quad to the mode
# selected in the IPexpress. This file is expected to be modified by the
# end user to adjust the PCSC quad to the final design requirements.

DEVICE_NAME "LFE2M50E"
PROTOCOL    "G8B10B" 
CH0_MODE    "SINGLE" 
CH1_MODE    "DISABLE" 
CH2_MODE    "DISABLE" 
CH3_MODE    "DISABLE" 
PLL_SRC     "CORE_TXREFCLK" 
DATARANGE     "MEDLOW" 
CH0_CDR_SRC     "CORE_RXREFCLK" 
CH0_DATA_WIDTH     "8" 
CH0_REFCK_MULT     "10X" 
#REFCLK_RATE     100
#FPGAINTCLK_RATE     100
CH0_TDRV_AMP     "0" 
CH0_TX_PRE     "DISABLE" 
CH0_RTERM_TX     "50" 
CH0_RX_EQ     "DISABLE" 
CH0_RTERM_RX     "50" 
CH0_RX_DCC     "AC" 
LOS_THRESHOLD     "0" 
PLL_TERM     "50" 
PLL_DCC     "AC" 
PLL_LOL_SET     "0" 
CH0_TX_SB     "NORMAL" 
CH0_RX_SB     "NORMAL" 
CH0_8B10B     "NORMAL" 
COMMA_A     "1100000101" 
COMMA_B     "0011111010" 
COMMA_M     "1111111111" 
CH0_COMMA_ALIGN     "AUTO" 
CH0_CTC_BYP     "BYPASS" 
CC_MATCH1     "0000000000" 
CC_MATCH2     "0000000000" 
CC_MATCH3     "0100011100" 
CC_MATCH4     "0100011100" 
CC_MATCH_MODE     "MATCH_4" 
CC_MIN_IPG     "0" 
CCHMARK     "4" 
CCLMARK     "4" 
OS_REFCK2CORE     "0"
OS_PLLQCLKPORTS     "0"
OS_INT_ALL     "0"

